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STK14CA8
128K x 8 AutoStoreTM nvSRAM QuantumTrapTM CMOS Nonvolatile Static RAM
FEATURES
* 25ns, 35ns and 45ns Access Times * "Hands-off" Automatic STORE on Power Down with only a small capacitor * STORE to QuantumTrapTM Nonvolatile Elements is Initiated by Software , device pin or AutoStoreTM on Power Down * RECALL to SRAM Initiated by Software or Power Up * Unlimited READ, WRITE and RECALL Cycles * 5mA Typical ICC at 200ns Cycle Time * 1,000,000 STORE Cycles to QuantumTrapTM * 100-Year Data Retention to QuantumTrapTM * Single 3V +20%, -10% Operation * Commercial and Industrial Temperatures * SOIC, SSOP and DIP Packages * RoHS Compliance
DESCRIPTION
The Simtek STK14CA8 is a fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate TM Simtek's QuantumTrap technology producing the world's most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent, nonvolatile data resides in the TM highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control.
BLOCK DIAGRAM
Quantum Trap 1024 X 1024 ROW DECODER STORE STATIC RAM ARRAY 1024 X 1024 RECALL VCC VCAP
A5 A6 A7 A8 A9 A12 A13 A14 A15 A16 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
POWER CONTROL STORE/ RECALL CONTROL
HSB
SOFTWARE DETECT INPUT BUFFERS COLUMN I/O COLUMN DEC
A15 - A0
A 0 A 1 A 2 A 3 A 4 A10 A11
G E W
Figure 1. Block Diagram
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PACKAGES
VCAP A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VCC A15 HSB W A13 A8 A9 A11 VCAP A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 HSB W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
VSS
VSS
DQ0 A3 A2 A1 A0 DQ1 DQ2
48 Pin SSOP
Relative PCB area usage. See website for detailed package size specifications.
PIN DESCRIPTIONS
Pin Name A16 - A0 DQ7 -DQ0 E W G VCC HSB I/O Input I/O Input Input Input Power Supply I/O Description Address: The 17 address inputs select one of 131,072 bytes in the nvSRAM array. Data: Bi-directional 8-bit data bus for accessing the nvSRAM. Chip Enable: The active low E Write Enable: The active low W the falling edge of E . Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G high causes the DQ pins to tri-state. Power 3.0V +20%, -10% Hardware Store Busy: When low this output indicates a Hardware Store is in progress. When pulled low external to the chip it will initiate a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin high if not connected. (Connection Optional) VCAP VSS (Blank) Power Supply Power Supply No Connect Autostore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements. Ground Unlabeled pins have no internal connection. input selects the device. enables data on the DQ pins to be written to the address location latched by
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SSOP
DQ6 G A10 E DQ7 DQ5 DQ4 DQ3 VCC
32 Pin SOIC or PDIP
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STK14CA8 ABSOLUTE MAXIMUM RATINGSa
-0.5V to +4.1V Power Supply Voltage -0.5V to (VCC + 0.5V) Voltage on Input Relative to VSS -0.5V to (VCC + 0.5V) Voltage on Outputs Temperature under Bias -55C to 125C Junction Temperature -55C to 140C Storage Temperature -65C to 150C Power Dissipation 1W DC Output Current (1 output at a time, 1s duration) 15mA
Notes a: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Package Thermal Characteristics see website: http://www.simtek.com/
DC CHARACTERISTICS
Symbol
ICC1
Parameter
Average VCC Current
Commercial MIN MAX
65 55 50
Industrial MIN MAX
70 60 55
Units
mA mA mA
Notes
tAVAV = 25ns tAVAV = 35ns tAVAV = 45ns Dependent on output loading and cycle rate. Values obtained without output loads. All Inputs Don't Care, VCC = max Average current for duration of STORE cycle (tSTORE). W (VCC - 0.2V) All Others Inputs Cycling, at CMOS Levels. Dependent on output loading and cycle rate. Values obtained without output loads. All Inputs Don't Care Average current for duration of STORE cycle (tSTORE). E (VCC - 0.2V) All Others VIN 0.2V or (VCC - 0.2V) Standby current level after nonvolatile cycle is complete. VCC = max
ICC2
Average VCC Current during STORE Average VCC Current at tAVAV = 200ns
3
3
mA
ICC3
3V, 25C, Typical Average VCAP Current during AutoStoreTM Cycle VCC Standby Current
5 3
5 3
mA mA
ICC4
ISB
(Standby, Stable CMOS Input Levels)
2
2
mA
IILK IOLK VIH VIL VOH VOL TA VCC VCAP
Input Leakage Current 1 Off-State Output Leakage Current 1 Input Logic "1" Voltage Input Logic "0" Voltage Output Logic "1" Voltage Output Logic "0" Voltage Operating Temperature Operating Voltage Storage Capacitor 0 2.7 17 2.0 VSS - 0.5 2.4 0.4 70 3.6 57 -40 2.7 17 VCC + 0.3 0.8 2.0 VSS - 0.5 2.4 0.4 85 3.6 57 1 VCC + 0.3 0.8 A V V V V
o
1
A
VIN = VSS to VCC VCC = max VIN = VSS to VCC, E or G VIH All Inputs All Inputs IOUT = -2mA IOUT = 4mA
C 3.0V +20%, -10% Between Vcap pin and Vss, 5V rated.
V F
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AC TEST CONDITIONS
0V to 3V Input Pulse Levels Input Rise and Fall Times 5ns Input and Output Timing Reference Levels 1.5V Output Load See Figure 2 and Figure 3
CAPACITANCE
SYMBOL CIN COUT
Notes
b
(TA = 25C, f = 1.0MHz)
MAX 7 7 UNITS pF pF CONDITIONS V = 0 to 3V V = 0 to 3V
PARAMETER Input Capacitance Output Capacitance
b: These parameters are guaranteed but not tested
3.0V 577 Ohms OUTPUT
789 Ohms
3.0V 577 Ohms OUTPUT 30 pF INCLUDING SCOPE AND FIXTURE
789 Ohms
5 pF 30 pF INCLUDING SCOPE AND FIXTURE
Figure 2. AC Output Loading
Figure 3. AC Output Loading, for tristate specs ( tHZ, tLZ, tWLQZ, tWHQZ, tGLQX, tGHQZ )
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SRAM READ CYCLES #1 & #2
SYMBOLS NO. #1 1 2 3 4 5 6 7 8 9 10 11
d tAXQX c tAVAV d
STK14CA8-25 PARAMETER Alt. tACS tRC tAA Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold after Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby 0 25 0 10 3 3 10 25 25 12 MIN MAX 25
STK14CA8-35 MIN MAX 35 35 35 15 3 3 13 0 13 0 35
STK14CA8-45 UNITS MIN MAX 45 45 45 20 3 3 15 0 15 0 45 ns ns ns ns ns ns ns ns ns ns ns
#2 tELQV
c tAVAV
tAVQV
tGLQV
tOE tOH
tELQX tEHQZ
e
tLZ tHZ tOLZ
e
tGLQX tGHQZ
tOHZ tPA tPS
tELICCb tEHICC
b
Notes c: W must be high during SRAM READ cycles d: Device is continuously selected with E and G both low e: Measured 200mV from steady state output voltage f: HSB must remain high during READ and WRITE cycles.
SRAM READ CYCLE #1: Address Controlledc,d,f
2 tAVAV
ADDRESS
5 tAXQX 3 tAVQV
DATA VALID
DQ (DATA OUT)
SRAM READ CYCLE #2: E Controlledc,f
2 tAVAV
ADDRESS
6 tELQX 7 tEHQZ 1 tELQV 11 tEHICCL
E
G
4 8 tGLQX 10 tELICCH ICC
STANDBY ACTIVE
tGLQV
9 tGHQZ
DQ (DATA OUT)
DATA VALID
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SRAM WRITE CYCLES #1 & #2
NO. #1 12 13 14 15 16 17 18 19 20 21 tAVAV tWLWH tELWH tDVWH tWHDX tAVWH tAVWL tWHAX tWLQZe,g tWHQX SYMBOLS #2 tAVAV tWLEH tELEH tDVEH tEHDX tAVEH tAVEL tEHAX Alt. tWC tWP tCW tDW tDH tAW tAS tWR tWZ tOW
Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Set-up to End of Write Data Hold after End of Write Address Set-up to End of Write Address Set-up to Start of Write Address Hold after End of Write Write Enable to Output Disable Output Active after End of Write
PARAMETER
STK14CA8-25 MIN 25 20 20 10 0 20 0 0 10 3 MAX
STK14CA8-35 MIN 35 25 25 12 0 25 0 0 13 3 MAX
STK14CA8-45 MIN 45 30 30 15 0 30 0 0 15 3 MAX
UNITS
ns ns ns ns ns ns ns ns ns ns
Notes g: If W is low when E goes low, the outputs remain in the high-impedance state. h: E or W must be VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlledh,f
12 tAVAV
ADDRESS
14 tELWH 19 tWHAX
E
17 tAVWH 13 tWLWH 15 tDVWH 16 tWHDX
18 tAVWL
W
DATA IN
20 tWLQZ
DATA VALID
DATA OUT
PREVIOUS DATA
HIGH IMPEDANCE
21 tWHQX
SRAM WRITE CYCLE #2: E Controlledh,f
12 tAVAV
ADDRESS
18 tAVEL 14 tELEH 19 tEHAX
E
17 tAVEH
W
13 tWLEH 15 tDVEH 16 tEHDX
DATA VALID HIGH IMPEDANCE
DATA IN DATA OUT
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MODE SELECTION
E H L L W X H L G X L X A15 - A0 X X X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8B45 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4B46 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8FC0 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4C63 MODE Not Selected Read SRAM Write SRAM Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Autostore Disable Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Autostore Enable Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Store Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Recall I/O Output High Z Output Data Input Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z POWER Standby Active Active NOTES
L
H
L
Active
i, j, k
L
H
L
Active
i, j, k
Active i, j, k ICC2
L
H
L
L
H
L
Active
i, j, k
Notes i: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle. j: While there are 17 addresses on the STK14CA8, only the lower 16 are used to control software modes k: I/O state depends on the state of G . The I/O table shown assumes G low.
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AutoStoreTM /POWER-UP RECALL
SYMBOLS NO. Standard 22 23 24 25 tHRECALL tSTORE VSWITCH tVCCRISE tHLHZ Alternate Power-up RECALL Duration STORE Cycle Duration Low Voltage Trigger Level 2.55 150 MIN MAX 20 12.5 2.65 ms ms V s l m PARAMETER STK14CA8 UNITS NOTES
VCC Rise Time Notes l: tHRECALL starts from the time VCC rises above VSWITCH m: If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place
AutoStoreTM/POWER-UP RECALL
VCC 24 VSWITCH
STORE occurs only if a SRAM write has happened.
No STORE occurs without at least one SRAM write.
25 tVCCRISE
AutoStoreTM
23 tSTORE
23 tSTORE
POWER-UP RECALL
22 tHRECALL
22 tHRECALL
Read & Write Inhibited
POWER-UP RECALL
BROWN OUT TM AutoStore
POWER-UP RECALL
POWER DOWN TM AutoStore
Note: Read and Write cycles will be ignored during STORE, RECALL and while VCC is below VSWITCH.
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SOFTWARE-CONTROLLED STORE/RECALL CYCLEn,o
SYMBOLS NO. E cont 26 27 28 29 tAVAV tAVEL tELEH tELAX G cont tAVAV tAVGL tGLGH tGLAX tRC tAS tCW STORE/RECALL Initiation Cycle Time Address Set-up Time Clock Pulse Width Address Hold Time 25 0 20 20 35 0 25 20 40 45 0 30 20 40 ns ns ns ns s o PARAMETER Alt. MIN MAX MIN MAX MIN MAX STK14CA8-25 STK14CA8-35 STK14CA8-45 UNITS NOTES
30 tRECALL tRECALL 40 RECALL Duration Notes n: The software sequence is clocked with E controlled READs or G controlled READs. o: The six consecutive addresses must be read in the order listed in the Mode Selection Table. W
must be high during all six consecutive cycles.
SOFTWARE STORE/RECALL CYCLE: E Controlledo
26 tAVAV ADDRESS 27 tAVEL
ADDRESS #1
26 tAVAV
ADDRESS #6
E
28 tELEH
G
29 tELAX
23 tSTORE DQ (DATA)
DATA VALID DATA VALID
/
30 tRECALL
HIGH IMPEDENCE
SOFTWARE STORE/RECALL CYCLE: G Controlledo
26 tAVAV ADDRESS
ADDRESS #1
26 tAVAV
ADDRESS #6
E
27 tAVGL
28 tGLGH
G
29 tGLAX DQ (DATA)
DATA VALID DATA VALID
23 tSTORE
/
30 tRECALL
HIGH IMPEDENCE
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HARDWARE STORE CYCLE
SYMBOLS NO. Standard 31 32 tDELAY tHLHX Alternate tHLQZ Time Allowed to Complete SRAM Cycle Hardware STORE Pulse Width PARAMETER MIN 1 15 300 MAX s ns ns p STK14CA8 UNITS NOTES
tHLBL Hardware STORE Low to STORE Busy 33 Notes p: Read and Write cycles in progress before HSB is asserted are given this amount of time to complete.
HARDWARE STORE CYCLE
32 tHLHX
HSB (IN)
23 tSTORE
HSB (OUT)
33 tHLBL
HIGH IMPEDENCE
HIGH IMPEDENCE
31 tDELAY DQ (DATA OUT)
DATA VALID DATA VALID
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DEVICE OPERATION
nvSRAM
The STK14CA8 nvSRAM is made up of two functional components paired in the same physical cell. These are a SRAM memory cell and a nonvolatile QuantumTrapTM cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM can be transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to SRAM (the RECALL operation). This unique architecture allows all cells to be stored and recalled in parallel. During the STORE and RECALL operations SRAM READ and WRITE operations are inhibited. The STK14CA8 supports unlimited reads and writes just like a typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to 1 million STORE operations.
SRAM WRITE
A WRITE cycle is performed whenever E and W are low and HSB is high. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-7 will be written into the memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on common I/O lines. If G is left low, internal circuitry will turn off the output buffers tWLQZ after W goes low.
AutoStoreTM OPERATION
The STK14CA8 stores data to nvSRAM using one of three storage operations. These three operations are Hardware Store, activated by HSB , Software Store, actived by an address sequence, and AutoStoreTM, on device power down. AutoStoreTM operation is a unique feature of Simtek QuantumTrapTM technology and is enabled by default on the STK14CA8. During normal operation, the device will draw current from Vcc to charge a capacitor connected to the Vcap pin. This stored charge will be used by the chip to perform a single STORE operation. If the voltage on the Vcc pin drops below Vswitch, the part will automatically disconnect the Vcap pin from Vcc. A STORE operation will be initiated with power provided by the Vcap capacitor. Figure 4 shows the proper connection of the storage capacitor (Vcap) for automatic store operation. Refer to the DC CHARACTERISTICS table for the size of Vcap. The voltage on the Vcap pin is driven to 5V by a charge pump internal to the chip. A pull up should be placed on W to hold it inactive during power up. To reduce unneeded nonvolatile stores, AutoStoreTM and Hardware Store operations will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place. The HSB signal can be monitored by the system to detect an AutoStoreTM cycle is in progress.
SRAM READ
The STK14CA8 performs a READ cycle whenever E and G are low while W and HSB are high. The address specified on pins A16-0 determines which of the 131,072 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E or G , the outputs will be valid at tELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought high, or W or HSB is brought low.
VCC VCAP VCC
10k Ohm
VCAP
W
Figure 4: AutoStoreTM Mode
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HARDWARE STORE ( HSB ) OPERATION
The STK14CA8 provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin can be used to request a hardware STORE cycle. When the HSB pin is driven low, the STK14CA8 will conditionally initiate a STORE operation after tDELAY. An actual STORE cycle will only begin if a WRITE to the SRAM took place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven low to indicate a busy condition while the STORE (initiated by any means) is in progress. SRAM READ and WRITE operations that are in progress when HSB is driven low by any means are given time to complete before the STORE operation is initiated. After HSB goes low, the STK14CA8 will continue SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations may take place. If a WRITE is in progress when HSB is pulled low it will be allowed a time, tDELAY, to complete. However, any SRAM WRITE cycles requested after HSB goes low will be inhibited until HSB returns high. During any STORE operation, regardless of how it was initiated, the STK14CA8 will continue to drive the HSB pin low, releasing it only when the STORE is complete. Upon completion of the STORE operation the STK14CA8 will remain disabled until the HSB pin returns high. If
HSB
SOFTWARE STORE
Data can be transferred from the SRAM to the nonvolatile memory by a software address sequence. The STK14CA8 software STORE cycle is initiated by executing sequential E controlled READ cycles from six specific address locations in exact order. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. Once a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence, or the sequence will be aborted and no STORE or RECALL will take place. To initiate the software STORE cycle, the following READ sequence must be performed:
1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8FC0 Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE cycle
The software sequence may be clocked with controlled READs or G controlled READs.
E
is not used, it should be left unconnected.
HARDWARE RECALL (POWER-UP)
During power up, or after any low-power condition (VCC < VSWITCH), an internal RECALL request will be latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle will automatically be initiated and will take tHRECALL to complete.
Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, although it is not necessary that G be low for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation.
SOFTWARE RECALL
Data can be transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of E controlled READ operations must be performed:
1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4C63 Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL cycle
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Internally, RECALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time the SRAM will once again be ready for READ and WRITE operations. The RECALL operation in no way alters the data in the nonvolatile elements.
NOISE CONSIDERATIONS
The STK14CA8 is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1F connected between VCC and VSS, using leads and traces that are as short as possible. As with all high-speed CMOS ICs, careful routing of power, ground and signals will reduce circuit noise.
PREVENTING AUTOSTORETM
The AutoStoreTM function can be disabled by initiating an AutoStore Disable sequence. A sequence of read operations is performed in a manner similar to the software STORE initiation. To initiate the AutoStore Disable sequence, the following sequence of E controlled read operations must be performed:
1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8B45 Valid READ Valid READ Valid READ Valid READ Valid READ AutoStore Disable
LOW AVERAGE ACTIVE POWER
CMOS technology provides the STK14CA8 this the benefit of drawing significantly less current when it is cycled at times longer than 50ns. Figure 5 shows the relationship between ICC and READ/WRITE cycle time. Worst-case current consumption is shown for commercial temperature range, VCC = 3.6V, and chip enable at maximum frequency. Only standby current is drawn when the chip is disabled. The overall average current drawn by the STK14CA8 depends on the following items: 1. 2. 3. 4. 5. 6. The duty cycle of chip enable. The overall cycle rate for accesses. The ratio of READs to WRITEs. The operating temperature. The VCC level. I/O loading.
The AutoStoreTM can be re-enabled by initiating an AutoStore Enable sequence. A sequence of read operations is performed in a manner similar to the software RECALL initiation. To initiate the AutoStore Enable sequence, the following sequence of E controlled read operations must be performed:
Average Active Current (mA)
1. 2. 3. 4. 5. 6.
Read address Read address Read address Read address Read address Read address
0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4B46
Valid READ Valid READ Valid READ Valid READ Valid READ AutoStore Enable
50 40 30 20 10 0 50 100 150 200 300 Cycle Time (ns)
Writes
If the AutoStoreTM function is disabled or re-enabled a manual STORE operation (Hardware or Software) needs to be issued to save the AutoStore state through subsequent power down cycles. The part comes from the factory with AutoStoreTM enabled.
DATA PROTECTION
The STK14CA8 protects data from corruption during low-voltage conditions by inhibiting all externally initiated STORE and WRITE operations. The lowvoltage condition is detected when VCC < VSWITCH . If the STK14CA8 is in a WRITE mode (both E and W low ) at power-up, after a RECALL, or after a STORE, the WRITE will be inhibited until a negative transition on E or W is detected. This protects against inadvertent writes during power up or brown out conditions.
Reads
Figure 5 Current vs. Cycle time
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ORDERING INFORMATION
STK14CA8 - R F 45 I
Temperature Range
Blank = Commercial (0 to 70C) I = Industrial (-40 to 85C)
Access Time
25 = 25ns 35 = 35ns 45 = 45ns
Lead Finish
Blank = 85% Sn / 15% Pb F = 100% Sn (Matte Tin) RoHS Compliant
Package
N = Plastic 32-pin 300 mil SOIC (50 mil pitch) R = Plastic 48-pin 300 mil SSOP (25 mil pitch) W = Plastic 32-pin 600 mil DIP (100 mil pitch)
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Document Revision History
Revision 0.0 0.1 0.2 Date January 2003 May 2003 September 2003
Summary Publish new datasheet Add 48 pin SSOP, Modify AutoStore drawing (Figure 2), Update Mode Selection Table and Absolute Maximum Ratings, Added G control software store Added lead-free lead finish
Parameter
Vcap Min tVCCRISE ICC1 Max Com. ICC1 Max Com. ICC1 Max Com. ICC1 Max Ind. ICC1 Max Ind. ICC1 Max Ind. ICC2 Max ICC4 Max tHRECALL tSTORE tRECALL tGLQV
Old Value
10F NA 35 mA 40 mA 50 mA 35 mA 45 mA 55 mA 1.5 mA 0.5 mA 5 ms 10 ms 20s 10ns
New Value
17 F 150 s 50 mA 55 mA 65 mA 55 mA 60 mA 70 mA 3.0 mA 3 mA 20 ms 12.5 ms 40s 12ns
Notes
New Spec @ 45ns access @ 35ns access @ 25ns access @ 45ns access @ 35ns access @ 25ns access Com. & Ind. Com & Ind.
1.0
December 2004
25 ns device
SIMTEK STK14CA8 Data Sheet, December 2004 Copyright 2004, Simtek Corporation. All rights reserved. This datasheet may only be printed for the express use of Simtek Customers. No part of this datasheet may be reproduced in any other form or means without express written permission from Simtek Corporation. The information contained in this publication is believed to be accurate, but changes may be made without notice. Simtek does not assume responsibility for, or grant or imply any warranty, including MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE regarding this information, the product or its use. Nothing herein constitutes a license, grant or transfer of any rights to any Simtek patent, copyright, trademark or other proprietary right.
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